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Brightness Ramp Control
When changing the group A brightness, the IC steps through
the brightness table at rate programmed by the RAMP
register, indicated in Table 2.
Register Addressing
The FAN5702 has six user-accessible registers.
Table 4. I 2 C Register Addresses
Table 2. Group A Brightness Ramp Control
Default Value
Address
RAMP[1:0] Time per Step
Full-Scale Ramp Time
7
6
5
4
3
2
1
0
HEX
00
01
10
11
0.1ms
25ms
50ms
100ms
6.4ms
1600ms
3200ms
6400ms
GENERAL
CONFIG
CHA
CH3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
10
20
A0
30
V OUT Short-Circuit Protection
The FAN5702 has integrated protection circuitry to prevent the
CH4
CH5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
40
50
device from being short circuited when the output voltage falls
below 2V. If this occurs, FAN5702 turns off the charge pump
and the LED driver outputs, but a small bypass switch is left
on. The device monitors the output voltage to determine if it is
still in short circuit condition and, once it has passed, soft-
starts and returns to normal operation.
Note:
7. Bold identifies bits that cannot be overwritten.
Bus Timing
CH6 1 1 1 1 1 1 1 1
60
As shown in Figure 19, data is normally transferred when SCL
I C Interface
V OUT Over-Voltage Protection
If the output voltage goes above 6V, the FAN5702 shuts down
until this condition has passed. The charge pump and LED
driver outputs are turned off. Once this condition has passed
FAN5702 soft-starts into normal operation.
2
is LOW. Data is clocked in to the FAN5702 on the rising edge
of SCL. Typically, data transitions shortly at or after the falling
edge of SCL to allow ample time for the data to set up before
the next SCL rising edge.
Data change allowed
The FAN5702 ’s serial interf ace is compatible with standard
and fast I 2 C bus specifications. The FAN5702 ’s SCL line is an
input and its SDA line is a bi-directional open-drain output,
meaning that it can only pull down the bus when active. The
SDA line only pulls LOW during data reads and when
signaling ACK. All data is shifted in MSB (bit 7) first.
SDA
SCL
T H
T SU
Slave Address
The FAN5702 ’s slave address is 6CH.
Table 3. I 2 C Slave Address
Figure 19. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
7
0
6
1
5
1
4
0
3
1
2
1
1
0
0
R/ W
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 20.
SDA
T HD;STA
Slave Address
MS Bit
SCL
Figure 20. Start Bit
? 2010 Fairchild Semiconductor Corporation
FAN5702 ? Rev. 1.0.4
13
www.fairchildsemi.com
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